W3DG72256V-D2 1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 3 2gb C 256mx72 sdram, register and spd, w/pll features burst mode operation auto and self refresh capability lvttl compatible inputs and outputs serial presence detect with eeprom fully synchronous: all signals are registered on the positive edge of the system clock programmable burst lengths: 1, 2, 4, 8 or full page 3.3v 0.3v power supply 168 pin dimm jedec ? pcb - d2: 37.34mm (1.47) description the w3dg72256v is a 256mx72 synchronous dram module which consists of eighteen 256mx4 stack sdram com po nents in tsop ii package, two 18 bit drive ics for input control signal and one 2kb eeprom in an 8 pin tssop package for serial presence detect which are mounted on a 168 pin dimm mul ti lay er fr4 substrate. * this product is subject to change without notice. note: consult factory for availability of: ? rohs compliant products ? vendor source control options ? industrial temperature option pin names a0 C a12 address input (multiplexed) ba0-1 select bank dq0-63 data input/output cb0-7 check bit (data-in/data-out) ck0 clock input cke0 clock enable input cs0#, cs3# chip select input ras# row address strobe cas# column address strobe we# write enable dqm0-7 dqm v cc power supply (3.3v) v ss ground *v ref power supply for reference rege register enable sda serial data i/o scl serial clock sa0-2 address in eeprom dnu do not use nc no connect * these pins are not used in this module. ** these pins should be nc in the system which does not support spd. pin configurations (front side/back side) pin front pin back pin front pin back pin back pin back 1v ss 29 dqm1 57 dq18 85 v ss 113 dqm5 141 dq50 2 dq0 30 cs0# 58 dq19 86 dq32 114 cs1# 142 dq51 3 dq1 31 dnu 59 v cc 87 dq33 115 ras# 143 v cc 4 dq2 32 v ss 60 dq20 88 dq34 116 v ss 144 dq52 5 dq3 33 a0 61 nc 89 dq35 117 a1 145 nc 6v cc 34 a2 62 *vref 90 v cc 118 a3 146 *v ref 7 dq4 35 a4 63 *cke1 91 dq36 119 a5 147 rege 8 dq5 36 a6 64 v ss 92 dq37 120 a7 148 v ss 9 dq6 37 a8 65 dq21 93 dq38 121 a9 149 dq53 10 dq7 38 a10/ap 66 dq22 94 dq39 122 ba0 150 dq54 11 dq8 39 ba1 67 dq23 95 dq40 123 a11 151 dq55 12 v ss 40 v cc 68 v ss 96 v ss 124 v cc 152 v ss 13 dq9 41 v cc 69 dq24 97 dq41 125 *ck1 153 dq56 14 dq10 42 ck0 70 dq25 98 dq42 126 a12 154 dq57 15 dq11 43 v ss 71 dq26 99 dq43 127 v ss 155 dq58 16 dq12 44 dnu 72 dq27 100 dq44 128 cke0 156 dq59 17 dq13 45 cs2# 73 v cc 101 dq45 129 cs3# 157 v cc 18 v cc 46 dqm2 74 dq28 102 v cc 130 dqm6 158 dq60 19 dq14 47 dqm3 75 dq29 103 dq46 131 dqm7 159 dq61 20 dq15 48 dnu 76 dq30 104 dq47 132 *a13 160 dq62 21 cb0 49 v cc 77 dq31 105 cb4 133 v cc 161 dq63 22 cb1 50 nc 78 v ss 106 cb5 134 nc 162 v ss 23 v ss 51 nc 79 *ck2 107 v ss 135 nc 163 *ck3 24 nc 52 cb2 80 nc 108 nc 136 cb6 164 nc 25 nc 53 cb3 81 nc 109 nc 137 cb7 165 **sa0 26 v cc 54 v ss 82 **sda 110 v cc 138 v ss 166 **sa1 27 we# 55 dq16 83 **scl 111 cas# 139 dq48 167 **sa2 28 dqm0 56 dq17 84 v cc 112 dqm4 140 dq49 168 v cc
W3DG72256V-D2 2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 3 functional block diagram rege pck dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 cs0# dqmb0 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqmb4 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqmb1 dqmb5 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqmb2 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqmb6 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqmb3 dqmb7 v cc v ss sdrams sdrams cb0 cb1 cb2 cb3 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 cb4 cb5 cb6 cb7 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 dqm cs i/o 0 i/o 1 i/o 2 i/o 3 * wire per clock loading table/wiring diagrams note: dq wiring may differ than described in this drawing, however dq/dqmb/cke/s relationships must be maintained as shown. ras#: sdrams cas#: sdrams cke0: sdrams we#: sdrams cs0#-cs3# dqmb0 to dqmb7 ba0-ba1 a0-a12 ras# cas# cke0 we# cke1 rs0#-rs3# rdqmb0-rdqmb7 rras# rcas# rcke0 rcke1 rwe# r e g i s t e r cke1: sdrams cs1# cs2# cs3# # rba0-rba1 ra0-ra12 ba0-ba1: sdrams a0-a12: sdrams a0 serial pd a1 a2 sa0 sa1 sa2 scl sda ck0 ck1 - ck3 12pf pll register sdram 12pf note: all resistor values are 10 ohms.
W3DG72256V-D2 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 3 absolute maximum ratings parameter symbol value units voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v cc supply relative to v ss v cc , v ccq -1.0 ~ 4.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 36 w short circuit current i os 50 ma note: permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. recommended dc operating conditions voltage referenced to: v ss = 0v, 0c t a 70 parameter symbol min typ max unit note supply voltage v cc 3.0 3.3 3.6 v input high voltage v ih 2.0 3.0 v ccq +0.3 v 1 input low voltage v il -0.3 0.8 v 2 output high voltage v oh 2.4 v i oh = -2ma output low voltage v ol 0.4 v i ol = -2ma input leakage current i li -10 10 a 3 note: 1. v ih (max)= 5.6v ac. the overshoot voltage duration is 3ns. 2. v il (min)= -2.0v ac. the undershoot voltage duration is 3ns. 3. any input 0v v in v ccq input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. capacitance t a = 25 c, f = 1mhz, v cc = 3.3v, v ref = 1.4v 200mv parameter symbol max unit input capacitance (a0-a12) c in1 9pf input capacitance (ras#,cas#,we#) c in2 9pf input capacitance (cke0) c in3 9pf input capacitance (clk0) c in4 17 pf input capacitance (cs0#,cs2#) c in5 9pf input capacitance (dqm0-dqm7) c in6 7pf input capacitance (ba0-ba1) c in7 9pf data input/output capacitance (dq0-dq63) c out 16 pf data input/output capacitance (cb0-cb7) c out1 16 pf
W3DG72256V-D2 4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 3 operating current characteristics v cc = 3.3v, 0c t a 70c notes: 1. measured with outputs open. 2. refresh period is 64ms. 3. measured with 1 pll & 2 drive ics. parameters symbol conditions versions units note 133/100 operating current (one bank active) i cc1 burst length = 1 t rc t rc (min) i ol = 0ma 7525 ma 1 precharge standby current in power down mode i cc2p c ke v il (max), t cc = 10ns 541 ma 3 i cc2ps c ke & clk v il (max), t cc = 450 ma 3 precharge standby current in non-power down mode i cc2n c ke v ih (min), cs v ih (min), t cc =10ns input signals are charged one time during 20 1405 ma 3 i cc2ns c ke v ih (min), clk v il (max), t cc = input signals are stable 468 ma 3 active standby current in power-down mode i cc3p c ke v il (max), t cc = 10ns 468 ma 3 i cc3ps c ke & clk v il (max), t cc = 375 ma 3 active standby in current non power- down mode i cc3n c ke v ih (min), cs v ih (min), t cc = 10ns input signals are charged one time during 20ns 2125 ma 3 i cc3ns c ke v ih (min), clk v il (max), t cc = input signals are stable 1487 ma 3 operating current (burst mode) i cc4 io = ma page burst 4 banks activated t ccd = 2clk 7525 ma 1 refresh current i cc5 t rc t rc (min) 12205 ma 2 self refresh current i cc6 c ke 0.2v 577 ma 3
W3DG72256V-D2 5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 3 * all dimensions are in millimeters and (inches) package dimensions for d2 3.99 (0.157) min. 6.60 (0.260) max. 1.27 0.10 (0.050 .004) 11.43 (0.450) 54.61 (2.150) 133.35 (5.250) 37.34 (1.470) 17.78 (0.700) 6.35 (0.250) 115.57 (4.550) (0.000) 36.83 (1.450) 6.35 (0.250) 57.79 (2.275) 3.18 (0.125) (2x) 3.99 (0.157 0.004) (2x) p1 (0.000) 3.10 (0.122) 8.89 (0.350) 15.60 (0.614) ordering information for d2 part number speed cas latency height* w3dg72256v10d2 100mhz cl=2 37.34 (1.47) w3dg72256v7d2 133mhz cl=2 37.34 (1.47) w3dg72256v75d2 133mhz cl=3 37.34 (1.47) notes: ? consult factory for availability of rohs compliant products. (g = rohs compliant) ? vendor speci? c part numbers are used to provide memory components source control. the place holder for this is shown as lo wer case x in the part numbers above and is to be replaced with the respective vendors code. consult factory for quali? ed sourcing options. (m = micron, s = samsung & consult f actory for others) ? consult factory for availability of industrial temperature (-40c to 85c) option
W3DG72256V-D2 6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 3 document title 2gb- 256mx72 sdram, register and spd, w/pll revision history rev # history release date status rev a created datasheet 11-6-01 advanced rev b b.1 corrected block diagram b.2 change module height to 1.10 1-22-02 advanced rev c c.1 pg. 5 corrected spec. pg. 6 corrected module width dimension 2.2 changed from advanced to preliminary 3-25-02 advanced rev 0 changed from advanced to final 9-19-02 final rev 1 changed mechanical package dimensions 1-22-04 final rev 2 2.1 updated cap and i dd specs 2.2 removed ed from part number 6-1-04 final rev 3 3.1 correction to module height changed from 1.10 to 1.47 8-05 final
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